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| mobile low-power sdr sdram mt48h8m16lf C 2 meg x 16 x 4 banks mt48h4m32lf C 1 meg x 32 x 4 banks features ? v dd /v ddq = 1.7C1.95v ? fully synchronous; all signals registered on positive edge of system clock ? internal, pipelined operation; column address can be changed every clock cycle ? 4 internal banks for concurrent operation ? programmable burst lengths (bl): 1, 2, 4, 8, and con- tinuous ? auto precharge, includes concurrent auto precharge ? auto refresh and self refresh modes ? lvttl-compatible inputs and outputs ? on-chip temperature sensor to control self refresh rate ? partial-array self refresh (pasr) ? deep power-down (dpd) ? selectable output drive strength (ds) ? 64ms refresh period options marking ? v dd /v ddq : 1.8v/1.8v h ? addressing C standard addressing option lf ? configuration C 8 meg x 16 (2 meg x 16 x 4 banks) 8m16 C 4 meg x 32 (1 meg x 32 x 4 banks) 4m32 ? plastic green packages C 54-ball vfbga (8mm x 8mm) 1 b4 C 90-ball vfbga (8mm x 13mm) 2 b5 ? timing: cycle time C 6ns at cl = 3 -6 C 7.5ns at cl = 3 -75 ? operating temperature range C commercial (0?c to +70?c) none C industrial (C40?c to +85?c) it ? revision :k notes: 1. available only for x16 configuration. 2. available only for x32 configuration. table 1: configuration addressing architecture 8 meg x 16 4 meg x 32 number of banks 4 4 bank address balls ba0, ba1 ba0, ba1 row address balls a[11:0] a[11:0] column address balls a[8:0] a[7:0] table 2: key timing parameters speed grade clock rate (mhz) access time cl = 2 cl = 3 cl = 2 cl = 3 -6 104 166 8ns 5ns -75 104 133 8ns 5.4ns note: 1. cl = cas (read) latency 128mb: 8 meg x 16, 4 meg x 32 mobile sdram features pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 1 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. products and specifications discussed herein are subject to change by micron without notice.
figure 1: 128mb mobile lpsdr part numbering mt 48 h 8m16 lf b4 -6 it :k micron technology product family 48 = mobile sdr sdram operating voltage h = 1.8v/1.8v configuration 8 meg x 16 4 meg x 32 addressing lf = mobile standard addressing revision :k operating t emperature blank = commercial (0c to +70c) it = industrial (C40c to +85c) cycle t ime -6 = 6ns, t ck cl = 3 -75 = 7.5ns, t ck cl = 3 package codes b4 = 8mm x 8mm vfbga green b5 = 8mm x 13mm vfbga green fbga part marking decoder due to space limitations, fbga-packaged components have an abbreviated part marking that is different from the part number. microns fbga part marking decoder is available at www.micron.com/decoder . 128mb: 8 meg x 16, 4 meg x 32 mobile sdram features pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 2 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. contents general description ......................................................................................................................................... 8 functional block diagram ................................................................................................................................ 9 ball assignments and descriptions ................................................................................................................. 10 package dimensions ...................................................................................................................................... 13 electrical specifications .................................................................................................................................. 15 absolute maximum ratings ........................................................................................................................ 15 electrical specifications C i dd parameters ........................................................................................................ 17 electrical specifications C ac operating conditions ......................................................................................... 20 output drive characteristics ........................................................................................................................... 23 functional description ................................................................................................................................... 26 commands .................................................................................................................................................... 27 command inhibit .................................................................................................................................. 28 no operation (nop) .............................................................................................................................. 28 load mode register (lmr) ................................................................................................................... 28 active ...................................................................................................................................................... 28 read ......................................................................................................................................................... 29 write ....................................................................................................................................................... 30 precharge .............................................................................................................................................. 31 burst terminate ................................................................................................................................... 31 auto refresh ......................................................................................................................................... 31 self refresh ........................................................................................................................................... 32 deep power-down ................................................................................................................................ 32 truth tables ................................................................................................................................................... 33 initialization .................................................................................................................................................. 38 mode register ................................................................................................................................................ 40 burst length .............................................................................................................................................. 41 burst type ................................................................................................................................................. 41 cas latency ............................................................................................................................................... 43 operating mode ......................................................................................................................................... 43 write burst mode ....................................................................................................................................... 43 extended mode register ................................................................................................................................. 44 temperature-compensated self refresh ..................................................................................................... 44 partial-array self refresh ............................................................................................................................ 45 output drive strength ................................................................................................................................ 45 bank/row activation ...................................................................................................................................... 46 read operation ............................................................................................................................................. 47 write operation ........................................................................................................................................... 56 burst read/single write .............................................................................................................................. 63 precharge operation .................................................................................................................................. 64 auto precharge ........................................................................................................................................... 64 auto refresh operation ............................................................................................................................. 76 self refresh operation .............................................................................................................................. 78 power-down .................................................................................................................................................. 80 deep power-down ......................................................................................................................................... 81 clock suspend ............................................................................................................................................... 82 revision history ............................................................................................................................................. 85 rev. g, production C 10/09 .......................................................................................................................... 85 rev. f, production C 8/09 ............................................................................................................................ 85 rev. e, production C 4/09 ............................................................................................................................ 85 rev. d, production C 10/08 .......................................................................................................................... 85 128mb: 8 meg x 16, 4 meg x 32 mobile sdram pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 3 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. rev. c, preliminary C 9/08 ........................................................................................................................... 85 rev. b, preliminary C 6/08 ........................................................................................................................... 85 rev. a, advance C 4/08 ................................................................................................................................ 85 revision history for commands, operations, and timing diagrams ............................................................. 85 update C 10/08 ........................................................................................................................................... 85 update C 7/08 ............................................................................................................................................ 85 update C 5/08 ............................................................................................................................................ 85 update C 4/08 ............................................................................................................................................ 86 128mb: 8 meg x 16, 4 meg x 32 mobile sdram pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 4 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. list of tables table 1: configuration addressing ................................................................................................................... 1 table 2: key timing parameters ...................................................................................................................... 1 table 3: vfbga ball descriptions .................................................................................................................. 12 table 4: absolute maximum ratings .............................................................................................................. 15 table 5: dc electrical characteristics and operating conditions ..................................................................... 15 table 6: capacitance ..................................................................................................................................... 16 table 7: i dd specifications and conditions (x16) ............................................................................................ 17 table 8: i dd specifications and conditions (x32) ............................................................................................ 17 table 9: i dd7 specifications and conditions (x16 and x32) ............................................................................... 18 table 10: electrical characteristics and recommended ac operating conditions ............................................ 20 table 11: ac functional characteristics ......................................................................................................... 21 table 12: target output drive characteristics (full strength) .......................................................................... 23 table 13: target output drive characteristics (three-quarter strength) .......................................................... 24 table 14: target output drive characteristics (one-half strength) ................................................................. 25 table 15: truth table C commands and dqm operation ................................................................................ 27 table 16: truth table C current state bank n , command to bank n ................................................................. 33 table 17: truth table C current state bank n, command to bank m ................................................................ 35 table 18: truth table C cke .......................................................................................................................... 37 table 19: burst definition table .................................................................................................................... 42 128mb: 8 meg x 16, 4 meg x 32 mobile sdram pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 5 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. list of figures figure 1: 128mb mobile lpsdr part numbering .............................................................................................. 2 figure 2: functional block diagram ................................................................................................................. 9 figure 3: 54-ball vfbga (top view) ............................................................................................................... 10 figure 4: 90-ball vfbga (top view) ............................................................................................................... 11 figure 5: 54-ball vfbga (8mm x 8mm) .......................................................................................................... 13 figure 6: 90-ball vfbga (8mm x 13mm) ......................................................................................................... 14 figure 7: typical self refresh current vs. temperature ................................................................................... 19 figure 8: active command .......................................................................................................................... 28 figure 9: read command ............................................................................................................................. 29 figure 10: write command ......................................................................................................................... 30 figure 11: precharge command ................................................................................................................ 31 figure 12: initialize and load mode register .................................................................................................. 39 figure 13: mode register definition ............................................................................................................... 40 figure 14: cas latency .................................................................................................................................. 43 figure 15: extended mode register definition ................................................................................................ 44 figure 16: example: meeting t rcd (min) when 2 < t rcd (min)/ t ck < 3 ......................................................... 46 figure 17: consecutive read bursts .............................................................................................................. 48 figure 18: random read accesses ................................................................................................................ 49 figure 19: read-to-write ............................................................................................................................ 50 figure 20: read-to-write with extra clock cycle ......................................................................................... 51 figure 21: read-to-precharge .................................................................................................................. 51 figure 22: terminating a read burst ............................................................................................................. 52 figure 23: alternating bank read accesses ..................................................................................................... 53 figure 24: read continuous page burst ........................................................................................................ 54 figure 25: read C dqm operation ................................................................................................................ 55 figure 26: write burst ................................................................................................................................. 56 figure 27: write-to-write .......................................................................................................................... 57 figure 28: random write cycles .................................................................................................................. 58 figure 29: write-to-read ............................................................................................................................ 58 figure 30: write-to-precharge ................................................................................................................. 59 figure 31: terminating a write burst ........................................................................................................... 60 figure 32: alternating bank write accesses .................................................................................................... 61 figure 33: write C continuous page burst .................................................................................................... 62 figure 34: write C dqm operation ............................................................................................................... 63 figure 35: read with auto precharge interrupted by a read ......................................................................... 65 figure 36: read with auto precharge interrupted by a write ....................................................................... 66 figure 37: read with auto precharge ............................................................................................................ 67 figure 38: read without auto precharge ....................................................................................................... 68 figure 39: single read with auto precharge .................................................................................................. 69 figure 40: single read without auto precharge ............................................................................................. 70 figure 41: write with auto precharge interrupted by a read ....................................................................... 71 figure 42: write with auto precharge interrupted by a write ...................................................................... 71 figure 43: write with auto precharge .......................................................................................................... 72 figure 44: write without auto precharge ..................................................................................................... 73 figure 45: single write with auto precharge ................................................................................................ 74 figure 46: single write without auto precharge ........................................................................................... 75 figure 47: auto refresh mode ........................................................................................................................ 77 figure 48: self refresh mode ......................................................................................................................... 79 figure 49: power-down mode ....................................................................................................................... 80 figure 50: clock suspend during write burst ............................................................................................... 82 128mb: 8 meg x 16, 4 meg x 32 mobile sdram pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 6 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. figure 51: clock suspend during read burst ................................................................................................ 83 figure 52: clock suspend mode ..................................................................................................................... 84 128mb: 8 meg x 16, 4 meg x 32 mobile sdram pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 7 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. general description the 128mb mobile lpsdr is a high-speed cmos, dynamic random access memory con- taining 134,217,728 bits. it is internally configured as a quad-bank dram with a synchro- nous interface (all signals are registered on the positive edge of the clock signal, clk). each of the x16s 33,554,432-bit banks is organized as 4096 rows by 512 columns by 16 bits. each of the x32s 33,554,432-bit banks is organized as 4096 rows by 256 columns by 32 bits. mobile lpsdr devices offer substantial advances in dram operating performance, in- cluding the ability to synchronously burst data at a high data rate with automatic column- address generation, the ability to interleave between internal banks to hide precharge time, and the capability to randomly change column addresses on each clock cycle dur- ing a burst access. note: 1. throughout the data sheet, various figures and text refer to dqs as dq. dq should be interpreted as any and all dq collectively, unless specifically stated otherwise. addition- ally, the x16 is divided into two bytes: the lower byte and the upper byte. for the lower byte (dq[7:0]), dqm refers to ldqm. for the upper byte (dq[15:8]), dqm refers to udqm. the x32 is divided into four bytes. for dq[7:0], dqm refers to dqm0. for dq[15:8], dqm refers to dqm1. for dq[23:16], dqm refers to dqm2, and for dq[31:24], dqm refers to dqm3. 2. complete functionality is described throughout the document; any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements. 3. any specific requirement takes precedence over a general statement. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram general description pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 8 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. functional block diagram figure 2: functional block diagram ras# cas# clk cs# we# cke control logic mode register command decode address ba0, ba1 dqm i/o gating dqm mask logic read data latch write drivers column decoder bank0 memory array bank0 row address latch and decoder sense amplifiers dq n bank1 bank2 bank3 2 2 ext mode register data output register data input register n n row address mux refresh counter address register bank control logic column/ address counter/ latch ba1 ba0 bank 0 0 0 0 1 1 1 0 2 1 1 3 128mb: 8 meg x 16, 4 meg x 32 mobile sdram functional block diagram pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 9 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. ball assignments and descriptions figure 3: 54-ball vfbga (top view) v ss dq14 dq12 dq10 dq8 udqm a1 2 a8 v ss dq15 dq13 dq11 dq9 dnu 1 clk a11 a7 a5 v ssq v ddq v ssq v ddq v ss cke a9 a6 a4 v ddq v ssq v ddq v ssq v dd cas# ba0 a0 a3 dq0 dq2 dq4 dq6 ldqm ras# ba1 a1 a2 v dd dq1 dq3 dq5 dq7 we# cs# a10 v dd a b c d e f g h j 1 2 3 4 5 6 7 8 9 note: 1. the e2 pin must be connected to v ss , v ssq , or left floating. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram ball assignments and descriptions pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 10 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. figure 4: 90-ball vfbga (top view) dq26 dq28 v ssq v ssq v ddq v ss a4 a7 clk dqm1 v ddq v ssq v ssq dq11 dq13 dq24 v ddq dq27 dq29 dq31 dqm3 a5 a8 cke dnu 1 dq8 dq10 dq12 v ddq dq15 v ss v ssq dq25 dq30 nc a3 a6 a12 a9 nc v ss dq9 dq14 v ssq v ss v dd v ddq dq22 dq17 nc a2 a10 a13 ba0 cas# v dd dq6 dq1 v ddq v dd dq23 v ssq dq20 dq18 dq16 dqm2 a0 ba1 cs# we# dq7 dq5 dq3 v ssq dq0 dq21 dq19 v ddq v ddq v ssq v dd a1 a11 ras# dqm0 v ssq v ddq v ddq dq4 dq2 a b c d e f g h j k l m n p r a b c d e f g h j k l m n p r 1 2 3 4 5 6 7 8 9 note: 1. the k2 pin must be connected to v ss , v ssq , or left floating. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram ball assignments and descriptions pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 11 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. table 3: vfbga ball descriptions symbol type description clk input clock: clk is driven by the system clock. all sdram input signals are sampled on the positive edge of clk. clk also increments the internal burst counter and controls the output registers. cke input clock enable: cke activates (high) and deactivates (low) the clk signal. deactivating the clock provides precharge power-down and self refresh operation (all banks idle), active power-down (row active in any bank), deep power-down (all banks idle), or clock suspend operation (burst/access in progress). cke is synchronous except after the device enters power- down and self refresh modes, where cke becomes asynchronous until after exiting the same mode. the input buffers, including clk, are disabled during power-down and self refresh modes, providing low standby power. cs# input chip select: cs# enables (registered low) and disables (registered high) the command decod- er. all commands are masked when cs# is registered high. cs# provides for external bank selection on systems with multiple banks. cs# is considered part of the command code. cas#, ras#, we# input command inputs: ras#, cas#, and we# (along with cs#) define the command being entered. ldqm,udq m(54-ball) dqm[3:0] (90-ball) input input/output mask: dqm is sampled high and is an input mask signal for write accesses and an output enable signal for read accesses. input data is masked during a write cycle. the output buffers are high-z (two-clock latency) during a read cycle. for the x16, ldqm corre- sponds to dq[7:0] and udqm corresponds to dq[16:8]. for the x32, dqm0 corresponds to dq[7:0], dqm1 corresponds to dq[15:8], dqm2 corresponds to dq[23:16], and dqm3 corre- sponds to dq[31:24]. dqm[3:0] (or ldqm and udqm if x16) are considered same state when referenced as dqm. ba0, ba1 input bank address input(s): ba0 and ba1 define to which bank the active, read, write, or pre- charge command is being applied. ba0 and ba1 become dont care when registering an all bank precharge (a10 high). a[13:0] input address inputs: addresses are sampled during the active command (row) and read/write command [column); column address a[9:0] (x16); with a10 defining auto precharge] to select one location out of the memory array in the respective bank. a10 is sampled during a pre- charge command to determine if all banks are to be precharged (a10 high) or bank selected by ba0, ba1. the address inputs also provide the op-code during a load mode reg- ister command. the maximum address range is dependent upon configuration. unused address pins become rfu. 1 dq[31:0] i/o data input/output: data bus. v ddq supply dq power: provide isolated power to dq for improved noise immunity. v ssq supply dq ground: provide isolated ground to dq for improved noise immunity. v dd supply core power supply. v ss supply ground. dnu C do not use: must be grounded or left floating. nc C internally not connected. these balls can be left unconnected but it is recommended that they be connected to v ss . note: 1. balls marked rfu may or may not be connected internally. these balls should not be used. contact the factory for details. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram ball assignments and descriptions pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 12 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. package dimensions figure 5: 54-ball vfbga (8mm x 8mm) ball a1 id 0.65 0.05 seating plane 0.1 a a 1 max 0.8 typ 0.8 typ 3.2 6.4 8 0.1 9 8 7 3 2 1 a b c d e f g h j 4 0.05 54x ?0.45 solder ball material: sac105 (98.5% sn, 1% ag, 0.5% cu) mold compound: epoxy novolac substrate material: plastic laminate 6.4 3.2 4 0.05 8 0.1 ball a1 id dimensions apply to solder balls post-reflow. pre- reflow balls are ?0.42 on ?0.4 smd ball pads. exposed plated features in all corners are floating nonbiased metal. note: 1. all dimensions are in millimeters. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram package dimensions pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 13 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. figure 6: 90-ball vfbga (8mm x 13mm) ball a1 id 1.0 max mold compound: epoxy novolac substrate material: plastic laminate solder ball material: sac105 (98.5% sn, 1%ag, 0.5% cu) 13 0.1 ball a1 id 9 8 7 3 2 1 a b c d e f g h j k l m n p r 0.8 typ 6.5 0.05 8 0.1 4 0.05 3.2 5.6 0.65 0.05 seating plane a 11.2 6.4 0.1 a 90x ?0.45 dimensions apply to solder balls post- reflow. pre-reflow balls are ?0.42 on ?0.4 smd ball pads. 0.8 typ note: 1. all dimensions are in millimeters. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram package dimensions pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 14 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. electrical specifications absolute maximum ratings stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. table 4: absolute maximum ratings voltage/temperature symbol min max unit voltage on v dd /v ddq supply relative to v ss v dd /v ddq 1 C0.35 +2.8 v voltage on inputs, nc, or i/o balls relative to v ss v in C0.35 +2.8 storage temperature (plastic) t stg C55 +150 ?c note: 1. v dd and v ddq must be within 300mv of each other at all times. v ddq must not exceed v dd . table 5: dc electrical characteristics and operating conditions notes 1 and 2 apply to all parameters and conditions; v dd /v ddq = 1.7C1.95v parameter/condition symbol min max unit notes supply voltage v dd 1.7 1.95 v i/o supply voltage v ddq 1.7 1.95 v input high voltage: logic 1; all inputs v ih 0.8 v ddq v ddq + 0.3 v 3 input low voltage: logic 0; all inputs v il C0.3 +0.3 v 3 output high voltage v oh 0.9 v ddq C v 4 output low voltage v ol C 0.2 v 4 input leakage current: any input 0v v in v dd (all other balls not under test = 0v) i l C1.0 1.0 a output leakage current: dq are disabled; 0v v out v ddq i oz C1.5 1.5 a operating temperature: industrial t a C40 +85 ?c commercial t a C40 +85 ?c notes: 1. all voltages referenced to v ss . 2. a full initialization sequence is required before proper device operation is ensured. 3. v ih overshoot: v ih,max = v ddq + 2v for a pulse width 3ns, and the pulse width cannot be greater than one-third of the cycle rate. v il undershoot: v il,min = C2v for a pulse width 3ns. 4. i out = 4ma for full drive strength. other drive strengths require appropriate scale. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram electrical specifications pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 15 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. table 6: capacitance note 1 applies to all parameters and conditions parameter symbol min max unit input capacitance: clk c l1 1.5 4.0 pf input capacitance: all other input-only balls c l2 1.5 4.0 pf input/output capacitance: dq c l0 3 5.0 pf note: 1. this parameter is sampled. v dd , v ddq = +1.8v; ta = 25?c; ball under test biased at 0.9v, f = 1 mhz. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram electrical specifications pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 16 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. electrical specifications C i dd parameters table 7: i dd specifications and conditions (x16) note 1 applies to all parameters and conditions; v dd /v ddq = 1.70C1.95v parameter/condition symbol max unit notes -6 -75 operating current: active mode; burst = 1; read or write; t rc = t rc (min) i dd1 50 40 ma 2, 3, 4 standby current: power-down mode; all banks idle; cke = low i dd2p 200 200 a 5 standby current: nonpower-down mode; all banks idle; cke = high i dd2n 15 12 ma standby current: active mode; cke = low; cs# = high; all banks active; no accesses in progress i dd3p 3 3 ma 3, 4, 6 standby current: active mode; cke = high; cs# = high; all banks active after t rcd met; no accesses in progress i dd3n 20 15 ma 3, 4, 6 operating current: burst mode; read or write; all banks active, half of dq toggling every cycle i dd4 80 70 ma 2, 3, 4 auto refresh current: cke = high; cs# = high t rfc = t rfc (min) i dd5 90 85 ma 2, 3, 4, 6 t rfc = 7.8125 s i dd6 5 3 ma 2, 3, 4, 7 deep power-down i zz 10 10 a 5, 8 table 8: i dd specifications and conditions (x32) note 1 applies to all parameters and conditions; v dd /v ddq = 1.70C1.95v parameter/condition symbol max unit notes -6 -75 operating current: active mode; burst = 1; read or write; t rc = t rc (min) i dd1 70 55 ma 2, 3, 4 standby current: power-down mode; all banks idle; cke = low i dd2p 200 200 a 5 standby current: nonpower-down mode; all banks idle; cke = high i dd2n 15 12 ma standby current: active mode; cke = low; cs# = high; all banks active; no accesses in progress i dd3p 3 3 ma 3, 4, 6 standby current: active mode; cke = high; cs# = high; all banks active after t rcd met; no accesses in progress i dd3n 20 15 ma 3, 4, 6 operating current: burst mode; read or write; all banks ac- tive, half of dq toggling every cycle i dd4 100 90 ma 2, 3, 4 auto refresh current: cke = high; cs# = high t rfc = t rfc (min) i dd5 90 85 ma 2, 3, 4, 6 t rfc = 7.8125 s i dd6 5 3 ma 2, 3, 4, 7 deep power-down i zz 10 10 a 5, 8 128mb: 8 meg x 16, 4 meg x 32 mobile sdram electrical specifications C i dd parameters pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 17 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. table 9: i dd7 specifications and conditions (x16 and x32) notes 1, 5, 9, and 10 apply to all parameters and conditions; v dd /v ddq = 1.70C1.95v parameter/condition symbol i dd7 unit self refresh: cke = low; t ck = t ck (min); address and control inputs are sta- ble; data bus inputs are stable full array, 85?c i dd7 200 a full array, 45?c 140 a 1/2 array, 85?c 160 a 1/2 array, 45?c 120 a 1/4 array, 85?c 140 a 1/4 array, 45?c 100 a 1/8 array, 85?c 120 a 1/8 array, 45?c 95 a 1/16 array, 85?c 100 a 1/16 array, 45?c 90 a notes: 1. a full initialization sequence is required before proper device operation is ensured. 2. i dd is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the outputs open. 3. the i dd current will increase or decrease proportionally according to the amount of fre- quency alteration for the test condition. 4. address transitions average one transition every 2 clocks. 5. measurement is taken 500ms after entering into this operating mode to provide tester measuring unit settling time. 6. other input signals can transition only one time for every 2 clocks and are otherwise at valid v ih or v il levels. 7. cke is high during the refresh command period t rfc (min) else cke is low. the i dd7 limit is a nominal value and does not result in a fail value. 8. typical values at 25?c (not a maximum value). 9. enables on-die refresh and address counters. 10. values for i dd7 85?c full array and partial array are guaranteed for the entire tempera- ture range. all other i dd7 values are estimated. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram electrical specifications C i dd parameters pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 18 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. figure 7: typical self refresh current vs. temperature full array 1/2 array 1/4 array 1/8 array 1/16 array C50 C40 C30 C20 C10 0 10 20 30 40 50 60 70 80 90 temperature (c) i dd7 (a) 120 100 80 60 40 20 0 128mb: 8 meg x 16, 4 meg x 32 mobile sdram electrical specifications C i dd parameters pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 19 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. electrical specifications C ac operating conditions table 10: electrical characteristics and recommended ac operating conditions notes 1C5 apply to all parameters and conditions parameter symbol -6 -75 unit notes min max min max access time from clk (positive edge) cl = 3 t ac C 5 C 5.4 ns cl = 2 C 8 C 8 address hold time t ah 1 C 1 C ns address setup time t as 1.5 C 1.5 C ns clk high-level width t ch 2.5 C 2.5 C ns clk low-level width t cl 2.5 C 2.5 C ns clock cycle time cl = 3 t ck 6 C 7.5 C ns 6 cl = 2 9.6 C 9.6 C cke hold time t ckh 1 C 1 C ns cke setup time t cks 1.5 C 1.5 C ns cs#, ras#, cas#, we#, dqm hold time t cmh 0.5 C 0.5 C ns cs#, ras#, cas#, we#, dqm setup time t cms 1.5 C 1.5 C ns data-in hold time t dh 1 C 1 C ns data-in setup time t ds 1.5 C 1.5 C ns data-out high-z time cl = 3 t hz C 5 C 5.4 ns 7 cl = 2 C 8 C 8 ns data-out low-z time t lz 1 C 1 C ns data-out hold time (load) t oh 2.5 C 2.5 C ns data-out hold time (no load) t ohn 1.8 C 1.8 C ns active-to-precharge command t ras 42 120,000 45 120,000 ns active-to-active command period t rc 60 C 67.5 C ns active-to-read or write delay t rcd 18 C 19.2 C ns refresh period t ref C 64 C 64 ms 8 auto refresh period t rfc 80 C 80 C ns precharge command period t rp 18 C 19.2 C ns active bank a to active bank b command t rrd 2 C 2 C t ck transition time t t 0.3 1.2 0.3 1.2 ns 9 write recovery time t wr 15 C 15 C ns 10 exit self refresh-to-active command t xsr 120 C 120 C ns 11 128mb: 8 meg x 16, 4 meg x 32 mobile sdram electrical specifications C ac operating conditions pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 20 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. table 11: ac functional characteristics notes 1C5 apply to all parameters and conditions parameter symbol -6 -75 unit notes last data-in to burst stop command t bdl 1 1 t ck 12 read/write command to read/write command t ccd 1 1 t ck 12 last data-in to new read/write command t cdl 1 1 t ck 12 cke to clock disable or power-down entry mode t cked 1 1 t ck 13 data-in to active command t dal 5 5 t ck 14, 16 data-in to precharge command t dpl 2 2 t ck 15, 16 dqm to input data delay t dqd 0 0 t ck 12 dqm to data mask during writes t dqm 0 0 t ck 12 dqm to data high-z during reads t dqz 2 2 t ck 12 write command to input data delay t dwd 0 0 t ck 12 load mode register command to active or refresh command t mrd 2 2 t ck cke to clock enable or power-down exit mode t ped 1 1 t ck 13 last data-in to precharge command t rdl 2 2 t ck 15, 16 data-out high-z from precharge command cl = 3 t roh 3 3 t ck 12 cl = 2 2 2 t ck notes: 1. a full initialization sequence is required before proper device operation is ensured. 2. the minimum specifications are used only to indicate cycle time at which proper opera- tion over the full temperature range (C40?c t a +85?c industrial temperature) is ensured. 3. in addition to meeting the transition rate specification, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 4. outputs measured for 1.8v at 0.9v with equivalent load: q 20pf test loads with full dq driver strength. performance will vary with actual system dq bus capacitive loading, termination, and programmed drive strength. 5. ac timing tests have v il and v ih with timing referenced to v ih/2 = crossover point. if the input transition time is longer than t tmax, then the timing is referenced at v il,max and v ih,min and no longer at the v ih/2 crossover point. 6. the clock frequency must remain constant (stable clock is defined as a signal cycling with- in timing constraints specified for the clock ball) during access or precharge states (read, write, including t wr, and precharge commands). cke may be used to reduce the data rate. 7. t hz defines the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 8. this device requires 4096 auto refresh cycles every 64ms ( t ref). providing a distrib- uted auto refresh command every 15.6 s meets the refresh requirement and ensures that each row is refreshed. alternatively, 4096 auto refresh commands can be issued in a burst at the minimum cycle rate ( t rfc), one time for every 64ms. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram electrical specifications C ac operating conditions pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 21 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. 9. ac characteristics assume t t = 1ns. for command and address input slew rates <0.5v/ns, timing must be derated. input setup times require an additional 50ps for each 100 mv/ ns reduction in slew rate. input hold times remain unchanged. if the slew rate exceeds 4.5v/ns, functionality is uncertain. 10. for auto precharge mode, the precharge timing budget ( t rp) begins at t rp C (1 t ckns), after the first clock delay and after the last write is executed. 11. clk must be toggled a minimum of two times during this period. 12. required clocks are specified by jedec functionality and are not dependent on any tim- ing parameter. 13. timing is specified by t cks. clock(s) specified as a reference only at minimum cycle rate. 14. timing is specified by t wr plus t rp. clock(s) specified as a reference only at minimum cycle rate. 15. timing is specified by t wr. 16. based on t ck (min), cl = 3. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram electrical specifications C ac operating conditions pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 22 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. output drive characteristics table 12: target output drive characteristics (full strength) notes 1C2 apply to all parameters and conditions; characteristics are specified under best and worst process variations/con- ditions voltage (v) pull-down current (ma) pull-up current (ma) min max min max 0.00 0.00 0.00 0.00 0.00 0.10 2.80 18.53 C2.80 C18.53 0.20 5.60 26.80 C5.60 C26.80 0.30 8.40 32.80 C8.40 C32.80 0.40 11.20 37.05 C11.20 C37.05 0.50 14.00 40.00 C14.00 C40.00 0.60 16.80 42.50 C16.80 C42.50 0.70 19.60 44.57 C19.60 C44.57 0.80 22.40 46.50 C22.40 C46.50 0.85 23.80 47.48 C23.80 C47.48 0.90 23.80 48.50 C23.80 C48.50 0.95 23.80 49.40 C23.80 C49.40 1.00 23.80 50.05 C23.80 C50.05 1.10 23.80 51.35 C23.80 C51.35 1.20 23.80 52.65 C23.80 C52.65 1.30 23.80 53.95 C23.80 C53.95 1.40 23.80 55.25 C23.80 C55.25 1.50 23.80 56.55 C23.80 C56.55 1.60 23.80 57.85 C23.80 C57.85 1.70 23.80 59.15 C23.80 C59.15 1.80 C 60.45 C C60.45 1.90 C 61.75 C C61.75 notes: 1. table values based on nominal impedance of 25 (full drive strength) at v ddq/2 . 2. the full variation in drive current, from minimum to maximum (due to process, voltage, and temperature) will lie within the outer bounding lines of the i-v curves. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram output drive characteristics pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 23 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. table 13: target output drive characteristics (three-quarter strength) notes 1 and 2 apply to all parameters and conditions; characteristics are specified under best and worst process variations/ conditions voltage (v) pull-down current (ma) pull-up current (ma) min max min max 0.00 0.00 0.00 0.00 0.00 0.10 1.96 12.97 C1.96 C12.97 0.20 3.92 18.76 C3.92 C18.76 0.30 5.88 22.96 C5.88 C22.96 0.40 7.84 25.94 C7.84 C25.94 0.50 9.80 28.00 C9.80 C28.00 0.60 11.76 29.75 C11.76 C29.75 0.70 13.72 31.20 C13.72 C31.20 0.80 15.68 32.55 C15.68 C32.55 0.85 16.66 33.24 C16.66 C33.24 0.90 16.66 33.95 C16.66 C33.95 0.95 16.66 34.58 C16.66 C34.58 1.00 16.66 35.04 C16.66 C35.04 1.10 16.66 35.95 C16.66 C35.95 1.20 16.66 36.86 C16.66 C36.86 1.30 16.66 37.77 C16.66 C37.77 1.40 16.66 38.68 C16.66 C38.68 1.50 16.66 39.59 C16.66 C39.59 1.60 16.66 40.50 C16.66 C40.50 1.70 16.66 41.41 C16.66 C41.41 1.80 C 42.32 C C42.32 1.90 C 43.23 C C43.23 notes: 1. table values based on nominal impedance of 37 (three-quarter drive strength) at v ddq/ 2 . 2. the full variation in drive current, from minimum to maximum (due to process, voltage, and temperature) will lie within the outer bounding lines of the i-v curves. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram output drive characteristics pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 24 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. table 14: target output drive characteristics (one-half strength) notes 1C3 apply to all parameters and conditions; characteristics are specified under best and worst process variations/con- ditions voltage (v) pull-down current (ma) pull-up current (ma) min max min max 0.00 0.00 0.00 0.00 0.00 0.10 1.27 8.42 C1.27 C8.42 0.20 2.55 12.30 C2.55 C12.30 0.30 3.82 14.95 C3.82 C14.95 0.40 5.09 16.84 C5.09 C16.84 0.50 6.36 18.20 C6.36 C18.20 0.60 7.64 19.30 C7.64 C19.30 0.70 8.91 20.30 C8.91 C20.30 0.80 10.16 21.20 C10.16 C21.20 0.85 10.80 21.60 C10.80 C21.60 0.90 10.80 22.00 C10.80 C22.00 0.95 10.80 22.45 C10.80 C22.45 1.00 10.80 22.73 C10.80 C22.73 1.10 10.80 23.21 C10.80 C23.21 1.20 10.80 23.67 C10.80 C23.67 1.30 10.80 24.14 C10.80 C24.14 1.40 10.80 24.61 C10.80 C24.61 1.50 10.80 25.08 C10.80 C25.08 1.60 10.80 25.54 C10.80 C25.54 1.70 10.80 26.01 C10.80 C26.01 1.80 C 26.48 C C26.48 1.90 C 26.95 C C26.95 notes: 1. table values based on nominal impedance of 55 (one-half drive strength) at v ddq/2 . 2. the full variation in drive current, from minimum to maximum (due to process, voltage, and temperature) will lie within the outer bounding lines of the i-v curves. 3. the i-v curve for one-quarter drive strength is approximately 50% of one-half drive strength. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram output drive characteristics pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 25 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. functional description mobile lpsdr devices are quad-bank dram that operate at 1.8v and include a synchro- nous interface. all signals are registered on the positive edge of the clock signal, clk. read and write accesses to the device are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed se- quence. accesses begin with the registration of an active command, followed by a read or write command. the address bits registered coincident with the active com- mand are used to select the bank and row to be accessed (ba0 and ba1 select the bank). the address bits registered coincident with the read or write command are used to select the starting column location for the burst access. the device provides for programmable read or write burst lengths. an auto pre- charge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. the device uses an internal pipelined architecture that enables changing the column address on every clock cycle to achieve high-speed, fully random access. precharging one bank while accessing one of the other three banks will hide the precharge cycles. the device is designed to operate in 1.8v memory systems. an auto refresh mode is pro- vided, along with power-saving, power-down, and deep power-down modes. all inputs and outputs are lvttl-compatible. the device offers substantial advances in dram operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time, and the capability to randomly change column addresses on each clock cycle dur- ing a burst access. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram functional description pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 26 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. commands the following table provides a quick reference of available commands, followed by a written description of each command. additional truth tables (table 16 (page 33), table 17 (page 35), and table 18 (page 37)) provide current state/next state informa- tion. table 15: truth table C commands and dqm operation note 1 applies to all parameters and conditions name (function) cs# ras# cas# we# dqm addr dq notes command inhibit (nop) h x x x x x x no operation (nop) l h h h x x x active (select bank and activate row) l l h h x bank/row x 2 read (select bank and column, and start read burst) l h l h l/h bank/col x 3 write (select bank and column, and start write burst) l h l l l/h bank/col valid 3 burst terminate or deep power-down (enter deep power-down mode) l h h l x x x 4, 5 precharge (deactivate row in bank or banks) l l h l x code x 6 auto refresh or self refresh (enter self refresh mode) l l l h x x x 7, 8 load mode register l l l l x op-code x 9 write enable/output enable x x x x l x active 10 write inhibit/output high-z x x x x h x high-z 10 notes: 1. cke is high for all commands shown except self refresh and deep power-down. 2. a[0 :n ] provide row address (where a n is the most significant address bit), ba0 and ba1 determine which bank is made active. 3. a[0 :i ] provide column address (where i = the most significant column address for a given device configuration). a10 high enables the auto precharge feature (nonpersistent), while a10 low disables the auto precharge feature. ba0 and ba1 determine which bank is being read from or written to. 4. this command is burst terminate when cke is high and deep power-down when cke is low. 5. the purpose of the burst terminate command is to stop a data burst, thus the com- mand could coincide with data on the bus. however, the dq column reads a dont care state to illustrate that the burst terminate command can occur when there is no data present. 6. a10 low: ba0, ba1 determine the bank being precharged. a10 high: all banks pre- charged and ba0, ba1 are dont care. 7. this command is auto refresh if cke is high, self refresh if cke is low. 8. internal refresh counter controls row addressing; all inputs and i/os are dont care except for cke. 9. a[11:0] define the op-code written to the mode register. 10. activates or deactivates the dq during writes (zero-clock delay) and reads (two-clock delay). 128mb: 8 meg x 16, 4 meg x 32 mobile sdram commands pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 27 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. command inhibit the command inhibit function prevents new commands from being executed by the device, regardless of whether the clk signal is enabled. the device is effectively de- selected. operations already in progress are not affected. no operation (nop) the no operation (nop) command is used to perform a nop to the selected device (cs# is low). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. load mode register (lmr) the mode registers are loaded via inputs a[ n:0] (where a n is the most significant ad- dress term), ba0, and ba1(see mode register (page 40)). the load mode register command can only be issued when all banks are idle and a subsequent executable com- mand cannot be issued until t mrd is met. active the active command is used to activate a row in a particular bank for a subsequent access. the value on the ba0, ba1 inputs selects the bank, and the address provided selects the row. this row remains active for accesses until a precharge command is issued to that bank. a precharge command must be issued before opening a differ- ent row in the same bank. figure 8: active command cs# we# cas# ras# cke clk address row address dont care high ba0, ba1 bank address 128mb: 8 meg x 16, 4 meg x 32 mobile sdram commands pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 28 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. read the read command is used to initiate a burst read access to an active row. the values on the ba0 and ba1 inputs select the bank; the address provided selects the starting column location. the value on input a10 determines whether auto precharge is used. if auto precharge is selected, the row being accessed is precharged at the end of the read burst; if auto precharge is not selected, the row remains open for subsequent accesses. read data appears on the dq subject to the logic level on the dqm inputs two clocks earlier. if a given dqm signal was registered high, the corresponding dq will be high- z two clocks later; if the dqm signal was registered low, the dq will provide valid data. figure 9: read command cs# we# cas# ras# cke clk column address a10 1 ba0, ba1 dont care high en ap dis ap bank address address note: 1. en ap = enable auto precharge, dis ap = disable auto precharge. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram commands pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 29 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. write the write command is used to initiate a burst write access to an active row. the val- ues on the ba0 and ba1 inputs select the bank; the address provided selects the starting column location. the value on input a10 determines whether auto precharge is used. if auto precharge is selected, the row being accessed is precharged at the end of the write burst; if auto precharge is not selected, the row remains open for subsequent accesses. input data appearing on the dq is written to the memory array, subject to the dqm input logic level appearing coincident with the data. if a given dqm signal is registered low, the corresponding data is written to memory; if the dqm signal is registered high, the corresponding data inputs are ignored and a write is not executed to that byte/column location. figure 10: write command dis ap en ap cs# we# cas# ras# cke clk column address dont care high bank address address ba0, ba1 valid address a10 1 note: 1. en ap = enable auto precharge, dis ap = disable auto precharge. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram commands pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 30 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a specified time ( t rp) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is precharged, inputs ba0 and ba1 select the bank. otherwise ba0 and ba1 are treated as dont care. after a bank has been precharged, it is in the idle state and must be activa- ted prior to any read or write commands are issued to that bank. figure 11: precharge command cs# we# cas# ras# cke clk a10 dont care high all banks bank selected address ba0, ba1 bank address valid address burst terminate the burst terminate command is used to truncate either fixed-length or continu- ous page bursts. the most recently registered read or write command prior to the burst terminate command is truncated. auto refresh auto refresh is used during normal operation and is analogous to cas#-before- ras# (cbr) refresh in fpm/edo dram. addressing is generated by the internal refresh controller. this makes the address bits dont care during an auto refresh command. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram commands pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 31 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. self refresh the self refresh command is used to place the device in self refresh mode. the self refresh mode is used to retain data in the sdram while the rest of the system is pow- ered down. when in self refresh mode, the device retains data without external clock- ing. the self refresh command is initiated like an auto refresh command, except that cke is disabled (low). after the self refresh command is registered, the inputs become dont care, with the exception of cke, which must remain low. deep power-down the deep power-down (dpd) command is used to enter deep power-down mode, achieving maximum power reduction by eliminating the power to the memory array. to enter dpd, all banks must be idle. while cke is low, hold cs# and we# low, and hold ras# and cas# high at the rising edge of the clock. to exit dpd, assert cke high. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram commands pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 32 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. truth tables table 16: truth table C current state bank n , command to bank n notes 1C6 apply to all parameters and conditions current state cs# ras# cas# we# command/action notes any h x x x command inhibit (nop/continue previous operation) l h h h no operation (nop/continue previous operation) idle l l h h active (select and activate row) l l l h auto refresh 7 l l l l load mode register 7 l l h l precharge 8 row active l h l h read (select column and start read burst) 9 l h l l write (select column and start write burst) 9 l l h l precharge (deactivate row in bank or banks) 10 read (auto precharge disabled) l h l h read (select column and start new read burst) 9 l h l l write (select column and start write burst) 9 l l h l precharge (truncate read burst, start precharge) 10 l h h l burst terminate 9, 11 write (auto precharge disabled) l h l h read (select column and start read burst) 9 l h l l write (select column and start new write burst) 9 l l h l precharge (truncate write burst, start precharge) 10 l h h l burst terminate 9, 11 notes: 1. this table applies when cke n-1 was high and cke n is high (see table 18 (page 37)) and after t xsr has been met (if the previous state was self refresh). 2. this table is bank-specific, except where noted (for example, the current state is for a specific bank and the commands shown can be issued to that bank when in that state). exceptions are covered below. 3. current state definitions: idle : the bank has been precharged, and t rp has been met. row active : a row in the bank has been activated, and t rcd has been met. no data bursts/ accesses and no register accesses are in progress. read : a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write : a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. the following states must not be interrupted by a command issued to the same bank. command inhibit or nop commands, or supported commands to the other bank should be issued on any clock edge occurring during these states. supported commands to any other bank are determined by the banks current state and the conditions descri- bed in this and the following table. precharging : starts with registration of a precharge command and ends when t rp is met. after t rp is met, the bank will be in the idle state. row activating : starts with registration of an active command and ends when t rcd is met. after t rcd is met, the bank will be in the row active state. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram truth tables pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 33 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. read with auto precharge enabled : starts with registration of a read command with auto precharge enabled and ends when t rp has been met. after t rp is met, the bank will be in the idle state. write with auto precharge enabled : starts with registration of a write command with auto precharge enabled and ends when t rp has been met. after t rp is met, the bank will be in the idle state. 5. the following states must not be interrupted by any executable command; command inhibit or nop commands must be applied on each positive clock edge during these states. refreshing : starts with registration of an auto refresh command and ends when t rfc is met. after t rfc is met, the device will be in the all banks idle state. accessing mode register : starts with registration of a load mode register com- mand and ends when t mrd has been met. after t mrd is met, the device will be in the all banks idle state. precharging all : starts with registration of a precharge all command and ends when t rp is met. after t rp is met, all banks will be in the idle state. 6. all states and sequences not shown are illegal or reserved. 7. not bank specific; requires that all banks are idle. 8. does not affect the state of the bank and acts as a nop to that bank. 9. reads or writes listed in the command/action column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 10. may or may not be bank specific; if all banks need to be precharged, each must be in a valid state for precharging. 11. this command is burst terminate when cke is high and deep power-down when cke is low. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram truth tables pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 34 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. table 17: truth table C current state bank n, command to bank m notes 1C6 apply to all parameters and conditions current state cs# ras# cas# we# command/action notes any h x x x command inhibit (nop/continue previous operation) l h h h no operation (nop/continue previous operation) idle x x x x any command otherwise supported for bank m row activating, active, or precharging l l h h active (select and activate row) l h l h read (select column and start read burst) 7 l h l l write (select column and start write burst) 7 l l h l precharge read (auto precharge disabled) l l h h active (select and activate row) l h l h read (select column and start new read burst) 7, 10 l h l l write (select column and start write burst) 7, 11 l l h l precharge 9 write (auto precharge disabled) l l h h active (select and activate row) l h l h read (select column and start read burst) 7, 12 l h l l write (select column and start new write burst) 7, 13 l l h l precharge 9 read (with auto precharge) l l h h active (select and activate row) l h l h read (select column and start new read burst) 7, 8, 14 l h l l write (select column and start write burst) 7, 8, 15 l l h l precharge 9 write (with auto precharge) l l h h active (select and activate row) l h l h read (select column and start read burst) 7, 8, 16 l h l l write (select column and start new write burst) 7, 8, 17 l l h l precharge 9 notes: 1. this table applies when cke n-1 was high and cke n is high (table 18 (page 37)), and after t xsr has been met (if the previous state was self refresh). 2. this table describes alternate bank operation, except where noted; for example, the cur- rent state is for bank n and the commands shown can be issued to bank m , assuming that bank m is in such a state that the given command is supported. exceptions are cov- ered below. 3. current state definitions: idle : the bank has been precharged, and t rp has been met. row active : a row in the bank has been activated, and t rcd has been met. no data bursts/ accesses and no register accesses are in progress. read : a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write : a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram truth tables pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 35 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. read with auto precharge enabled : starts with registration of a read command with auto precharge enabled and ends when t rp has been met. after t rp is met, the bank will be in the idle state. write with auto precharge enabled : starts with registration of a write command with auto precharge enabled and ends when t rp has been met. after t rp is met, the bank will be in the idle state. 4. auto refresh, self refresh, and load mode register commands can only be is- sued when all banks are idle. 5. a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. all states and sequences not shown are illegal or reserved. 7. reads or writes to bank m listed in the command/action column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 8. concurrent auto precharge: bank n will initiate the auto precharge command when its burst has been interrupted by bank m burst. 9. the burst in bank n continues as initiated. 10. for a read without auto precharge interrupted by a read (with or without auto pre- charge), the read to bank m will interrupt the read on bank n , cas latency (cl) later. 11. for a read without auto precharge interrupted by a write (with or without auto pre- charge), the write to bank m will interrupt the read on bank n when registered. dqm should be used one clock prior to the write command to prevent bus contention. 12. for a write without auto precharge interrupted by a read (with or without auto pre- charge), the read to bank m will interrupt the write on bank n when registered, with the data-out appearing cl later. the last valid write to bank n will be data-in regis- tered one clock prior to the read to bank m . 13. for a write without auto precharge interrupted by a write (with or without auto pre- charge), the write to bank m will interrupt the write on bank n when registered. the last valid write to bank n will be data-in registered one clock prior to the read to bank m . 14. for a read with auto precharge interrupted by a read (with or without auto pre- charge), the read to bank m will interrupt the read on bank n , cl later. the pre- charge to bank n will begin when the read to bank m is registered. 15. for a read with auto precharge interrupted by a write (with or without auto pre- charge), the write to bank m will interrupt the read on bank n when registered. dqm should be used two clocks prior to the write command to prevent bus contention. the precharge to bank n will begin when the write to bank m is registered. 16. for a write with auto precharge interrupted by a read (with or without auto pre- charge), the read to bank m will interrupt the write on bank n when registered, with the data-out appearing cl later. the precharge to bank n will begin after t wr is met, where t wr begins when the read to bank m is registered. the last valid write bank n will be data-in registered one clock prior to the read to bank m . 17. for a write with auto precharge interrupted by a write (with or without auto pre- charge), the write to bank m will interrupt the write on bank n when registered. the precharge to bank n will begin after t wr is met, where t wr begins when the write to bank m is registered. the last valid write to bank n will be data registered one clock to the write to bank m . 128mb: 8 meg x 16, 4 meg x 32 mobile sdram truth tables pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 36 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. table 18: truth table C cke notes 1C4 apply to all parameters and conditions current state cke n-1 cke n command n action n notes power-down l l x maintain power-down self refresh x maintain self refresh clock suspend x maintain clock suspend deep power-down x maintain deep power-down power-down l h command inhibit or nop exit power-down 5 deep power-down x exit deep power-down self refresh command inhibit or nop exit self refresh 6 clock suspend x exit clock suspend 7 all banks idle h l command inhibit or nop power-down entry all banks idle burst terminate deep power-down entry 8 all banks idle auto refresh self refresh entry reading or writing valid clock suspend entry h h table 17 (page 35) notes: 1. cke n is the logic state of cke at clock edge n; cke n-1 was the state of cke at the previ- ous clock edge. 2. current state is the state of the sdram immediately prior to clock edge n . 3. command n is the command registered at clock edge n , and action n is a result of com- mand n . 4. all states and sequences not shown are illegal or reserved. 5. exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided that t cks is met). 6. exiting self refresh at clock edge n will put the device in the all banks idle state after t xsr is met. command inhibit or nop commands should be issued on any clock edges occurring during the t xsr period. a minimum of two nop commands must be provided during the t xsr period. 7. after exiting clock suspend at clock edge n , the device will resume operation and recog- nize the next command at clock edge n + 1. 8. deep power-down is a power-saving feature of this device. this command is burst ter- minate when cke is high and deep power-down when cke is low. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram truth tables pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 37 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. initialization low-power sdram devices must be powered up and initialized in a predefined man- ner. using initialization procedures other than those specified may result in undefined operation. after power is simultaneously applied to v dd and v ddq and the clock is sta- ble (a stable clock is defined as a signal cycling within timing constraints specified for the clock ball), the device requires a 100 s delay prior to issuing any command other than a command inhibit or nop. starting at some point during this 100 s period and continuing at least through the end of this period, command inhibit or nop commands should be applied. after the 100 s delay is satisfied by issuing at least one command inhibit or nop command, a precharge command must be issued. all banks must then be pre- charged, which places the device in the all banks idle state. when in the idle state, two auto refresh cycles must be performed. after the auto refresh cycles are complete, the device is ready for mode register programming. be- cause the mode register powers up in an unknown state, it should be loaded prior to issuing any operational command. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram initialization pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 38 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. figure 12: initialize and load mode register cke ba0, ba1 load extended mode register load mode register t cks powe r -up: v dd and clk stable t = 100s t ckh ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dqm ( ) ( ) ( ) ( ) dq high-z address valid a10 valid clk t ck command 1 ar nop lmr ar lmr valid t cms t cmh t as t ah ba0 = l, ba1 = l ( ) ( ) ( ) ( ) code code t as t ah code code ( ) ( ) ( ) ( ) pre all banks t as t ah ( ) ( ) ( ) ( ) t0 t1 dont care ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t rp t mrd 3 t mrd 3 t rfc 2 t rfc 2 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) valid ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ba0 = l, ba1 = l ba0 = l, ba1 = h ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) precharge all banks ( ) ( ) ( ) ( ) tn + 1 to + 1 tp + 1 tq + 1 tr + 1 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) notes: 1. pre = precharge command, ar = auto refresh command, lmr = load mode regis- ter command. 2. nops or deselects must only be provided during t rfc time. 3. nops or deselects must only be provided during t mrd time. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram initialization pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 39 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. mode register the mode register defines the specific mode of operation, including burst length (bl), burst type, cas latency (cl), operating mode, and write burst mode. the mode register is programmed via the load mode register command and retains the stored infor- mation until it is programmed again or the device loses power. mode register bits m[2:0] specify the bl; m3 specifies the type of burst; m[6:4] specify the cl; m7 and m8 specify the operating mode; m9 specifies the write burst mode; and m10Cm n should be set to zero to ensure compatibility with future revisions. m n + 1 and m n + 2 should be set to zero to select the mode register. the mode registers must be loaded when all banks are idle, and the controller must wait t mrd before initiating the subsequent operation. violating either of these require- ments will result in unspecified operation. figure 13: mode register definition *should be programmed to 0 to ensure compatibility with future devices. m3 = 0 1 2 4 8 reserved reserved reserved continuous m3 = 1 2 4 8 reserved reserved reserved reserved 1 0 1 burst type sequential interleaved cas latency reserved reserved 2 3 reserved reserved reserved reserved burst length m0 0 1 0 1 0 1 0 1 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 mode register (mx) address bus 9 7 6 5 4 3 8 2 1 burst length cas latency bt op mode reserved* wb 0 a n m n a10 m10 ... ... a9 m9 a8 m8 a7 m7 a6 m6 a5 m5 a4 m4 a3 m3 a2 m2 a1 m1 a0 m0 10 ... n ba0 m n+1 ba1 m n+2 0 n+2 n+1 0 m8 0 C m7 0 C operating mode mode register definition base mode register reserved extended mode register reserved m n+2 m n+1 m9 0 1 write burst mode programmed burst length single location access normal operation all other states reserved 128mb: 8 meg x 16, 4 meg x 32 mobile sdram mode register pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 40 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. burst length read and write accesses to the device are burst oriented, and the burst length (bl) is programmable. the burst length determines the maximum number of column loca- tions that can be accessed for a given read or write command. burst lengths of 1, 2, 4, 8, or continuous locations are available for both the sequential and the interleaved burst types, and a continuous page burst is available for the sequential type. the contin- uous page burst is used in conjunction with the burst terminate command to generate arbitrary burst lengths. reserved states should not be used, as unknown operation or incompatibility with fu- ture versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst wraps within the block when a boundary is reached. the block is uniquely selected by a[8:1] when bl = 2, a[8:2] when bl = 4, and a[8:3] when bl = 8. the remaining (least significant) address bit(s) is (are) used to select the starting loca- tion within the block. continuous page bursts wrap within the page when the boundary is reached. burst type accesses within a given burst can be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram mode register pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 41 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. table 19: burst definition table burst length starting column address order of accesses within a burst type = sequential type = interleaved 2 a0 0 0-1 0-1 1 1-0 1-0 4 a1 a0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 continuous n = a0Can/9/8 (location 0Cy) cn, cn + 1, cn + 2, cn + 3...cn - 1, cn... not supported 128mb: 8 meg x 16, 4 meg x 32 mobile sdram mode register pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 42 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. cas latency the cas latency (cl) is the delay, in clock cycles, between the registration of a read command and the availability of the output data. the latency can be set to two or three clocks. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available by clock edge n + m . the dq start driving as a result of the clock edge one cycle earlier ( n + m - 1), and provided that the relevant access times are met, the data is valid by clock edge n + m . for example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at t0 and the latency is programmed to two clocks, the dq start driving after t1 and the data is valid by t2. reserved states should not be used as unknown operation or incompatibility with fu- ture versions may result. figure 14: cas latency clk dq t2 t1 t3 t0 cl = 3 t lz d out t oh command nop read nop t4 nop dont care undefined clk dq t2 t1 t3 t0 cl = 2 t lz d out t oh command nop read t ac t ac nop operating mode the normal operating mode is selected by setting m7 and m8 to zero; the other combi- nations of values for m7 and m8 are reserved for future use. reserved states should not be used because unknown operation or incompatibility with future versions may result. write burst mode when m9 = 0, the burst length programmed via m[2:0] applies to both read and write bursts; when m9 = 1, the programmed burst length applies to read bursts, but write accesses are single-location (nonburst) accesses. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram mode register pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 43 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. extended mode register the extended mode register (emr) controls additional functions beyond those control- led by the mode register. these additional functions include tcsr, pasr, and output drive strength. the emr is programmed via the lmr command (ba1 = 1, ba0 = 0) and retains the stor- ed information until it is programmed again or the device loses power. the emr must be programmed with e[ n:7] set to 0. it must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. violating either of these requirements re- sults in unspecified operation. after the values are entered, the emr settings are re- tained even after exiting deep power-down mode. figure 15: extended mode register definition extended mode register (ex) address bus 9 7 6 5 4 3 8 2 1 pasr tcsr 1 ds operation 0 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 10 ... e2 0 0 0 0 1 1 1 1 e1 0 0 1 1 0 0 1 1 e0 0 1 0 1 0 1 0 1 partial-array self refresh coverage full array 1/2 array 1/4 array reserved reserved 1/8 array 1/16 array reserved ba0 ... ba1 1 n n + 1 n + 2 0 e10 0 C ... 0 C e n 0 C e9 0 e8 0 C normal ar operation all other states reserved a n e6 0 0 1 1 0 0 1 1 e7 0 0 0 0 1 1 1 1 e5 0 1 0 1 0 1 0 1 drive strength full strength 1/2 strength 1/4 strength 3/4 strength 3/4 strength reserved reserved reserved e7Ce0 valid C C e n + 2 0 0 1 1 e n + 1 0 1 0 1 mode register definition standard mode register status register extended mode register reserved note: 1. on-die temperature sensor is used in place of tcsr. setting these bits will have no effect. temperature-compensated self refresh this device includes a temperature sensor that is implemented for automatic control of the self refresh oscillator. programming the temperature-compensated self refresh (tcsr) bits has no effect on the device. the self refresh oscillator will continue refresh at the optimal factory-programmed rate for the device temperature. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram extended mode register pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 44 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. partial-array self refresh for further power savings during self refresh, the partial-array self refresh (pasr) fea- ture enables the controller to select the amount of memory to be refreshed during self refresh. the refresh options are: ? full array: banks 0, 1, 2, and 3 ? one-half array: banks 0 and 1 ? one-quarter array: bank 0 ? one-eighth array: bank 0 with row address most significant bit (msb) = 0 ? one-sixteenth array: bank 0 with row address msb = 0 and row address msb - 1 = 0 read and write commands can still be issued to any bank selected during standard operation, but only the selected banks or segments of a bank in pasr are refreshed dur- ing self refresh. it is important to note that data in unused banks or portions of banks is lost when pasr is used. output drive strength because the device is designed for use in smaller systems that are typically point-to- point connections, an option to control the drive strength of the output buffers is provided. drive strength should be selected based on the expected loading of the mem- ory bus. there are four supported settings for the output drivers: 25, 37, 55, and 80 internal impedance. these are full, three-quarter, one-half, and one-quarter drive strengths, respectively. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram extended mode register pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 45 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. bank/row activation before any read or write commands can be issued to a bank within the sdram, a row in that bank must be opened. this is accomplished via the active command, which selects both the bank and the row to be activated. after a row is opened with the active command, a read or write command can be issued to that row, subject to the t rcd specification. t rcd (min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which a read or write command can be entered. for example, a t rcd specification of 20ns with a 125 mhz clock (8ns period) results in 2.5 clocks, rounded to 3. this is reflected in figure 16 (page 46), which cov- ers any case where 2 < t rcd (min)/ t ck 3. (the same procedure is used to convert other specification limits from time units to clock cycles.) a subsequent active command to a different row in the same bank can only be issued after the previous active row has been precharged. the minimum time interval between successive active commands to the same bank is defined by t rc. a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. the mini- mum time interval between successive active commands to different banks is defined by t rrd. figure 16: example: meeting t rcd (min) when 2 < t rcd (min)/ t ck < 3 clk t2 t1 t3 t0 t command nop active read or write nop rcd(min) t ck t ck t ck dont care 128mb: 8 meg x 16, 4 meg x 32 mobile sdram bank/row activation pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 46 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. read operation read bursts are initiated with a read command, as shown in figure 9 (page 29). the starting column and bank addresses are provided with the read command, and auto precharge is either enabled or disabled for that burst access. if auto precharge is ena- bled, the row being accessed is precharged at the completion of the burst. in the following figures, auto precharge is disabled. during read bursts, the valid data-out element from the starting column address is available following the cas latency after the read command. each subsequent data- out element will be valid by the next positive clock edge. figure 18 (page 49) shows general timing for each possible cas latency setting. upon completion of a burst, assuming no other commands have been initiated, the dq signals will go to high-z. a continuous page burst continues until terminated. at the end of the page, it wraps to column 0 and continues. data from any read burst can be truncated with a subsequent read command, and data from a fixed-length read burst can be followed immediately by data from a read command. in either case, a continuous flow of data can be maintained. the first data element from the new burst either follows the last element of a completed burst or the last desired data element of a longer burst that is being truncated. the new read com- mand should be issued x cycles before the clock edge at which the last desired data element is valid, where x = cl - 1. this is shown in figure 18 (page 49) for cl2 and cl3. mobile lpsdr devices use a pipelined architecture and therefore do not require the 2 n rule associated with a prefetch architecture. a read command can be initiated on any clock cycle following a read command. full-speed random read accesses can be per- formed to the same bank, or each subsequent read can be performed to a different bank. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram read operation pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 47 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. figure 17: consecutive read bursts dont care clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read x = 1 cycle cl = 2 clk dq d out t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop bank, col b d out d out d out d out read nop t7 cl = 3 transitioning data x = 2 cycles note: 1. each read command can be issued to any bank. dqm is low. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram read operation pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 48 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. figure 18: random read accesses clk dq t2 t1 t4 t3 t6 t5 t0 command address dont care d out d out d out d out clk dq t2 t1 t4 t3 t5 t0 command address read nop bank, col n read read read nop bank, col a bank, col x bank, col m read nop bank, col n bank, col a read read read nop nop bank, col x bank, col m cl = 2 cl = 3 d out d out d out d out note: 1. each read command can be issued to any bank. dqm is low. data from any read burst can be truncated with a subsequent write command, and data from a fixed-length read burst can be followed immediately by data from a write command (subject to bus turnaround limitations). the write burst can be initi- ated on the clock edge immediately following the last (or last desired) data element from the read burst, provided that i/o contention can be avoided. in a given system design, there is a possibility that the device driving the input data will go low-z before the dq go high-z. in this case, at least a single-cycle delay should occur between the last read data and the write command. the dqm input is used to avoid i/o contention, as shown in figure 19 (page 50) and figure 20 (page 51). the dqm signal must be asserted (high) at least two clocks prior to the write command (dqm latency is two clocks for output buffers) to suppress data- out from the read. after the write command is registered, the dq will go to high-z (or remain high-z), regardless of the state of the dqm signal, provided the dqm was active on the clock just prior to the write command that truncated the read com- mand. if not, the second write will be an invalid write. for example, if dqm was low during t4, then the writes at t5 and t7 would be valid, and the write at t6 would be invalid. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram read operation pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 49 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. the dqm signal must be de-asserted prior to the write command (dqm latency is zero clocks for input buffers) to ensure that the written data is not masked. figure 19 (page 50) shows where, due to the clock cycle frequency, bus contention is avoided without having to add a nop cycle, while figure 20 (page 51) shows the case where an additional nop cycle is required. a fixed-length read burst may be followed by or truncated with a precharge com- mand to the same bank, provided that auto precharge was not activated. the pre- charge command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = cl - 1. this is shown in figure 21 (page 51) for each possible cl; data element n + 3 is either the last of a burst of four or the last de- sired data element of a longer burst. following the precharge command, a subse- quent command to the same bank cannot be issued until t rp is met. note that part of the row precharge time is hidden during the access of the last data element(s). in the case of a fixed-length burst being executed to completion, a precharge com- mand issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. the disadvant- age of the precharge command is that it requires that the command and address buses be available at the appropriate time to issue the command. the advantage of the precharge command is that it can be used to truncate fixed-length or continuous page bursts. figure 19: read-to-write read nop nop write nop clk t2 t1 t4 t3 t0 dqm dq command address bank, col b bank, col n ds t hz t ck dont care transitioning data t d out d in note: 1. cl = 3. the read command can be issued to any bank, and the write command can be to any bank. if a burst of one is used, dqm is not required. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram read operation pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 50 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. figure 20: read-to-write with extra clock cycle dont care read nop nop nop nop dqm clk dq d out t2 t1 t4 t3 t0 command address bank, col n write d in bank, col b t5 t ds t hz transitioning data note: 1. cl = 3. the read command can be issued to any bank, and the write command can be to any bank. figure 21: read-to-precharge dont care clk dq t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop nop precharge active t rp t7 clk dq d out t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop nop d out d out d out precharge active t rp t7 x = 1 cycle cl = 2 cl = 3 x = 2 cycles bank a , col n bank a , row bank ( a or all) bank a , col bank a , row bank ( a or all) transitioning data d out d out d out d out note: 1. dqm is low. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram read operation pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 51 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. continuous-page read bursts can be truncated with a burst terminate command and fixed-length read bursts can be truncated with a burst terminate command, provided that auto precharge was not activated. the burst terminate command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = cl - 1. this is shown in figure 22 (page 52) for each possible cas latency; data element n + 3 is the last desired data element of a longer burst. figure 22: terminating a read burst clk dq t2 t1 t4 t3 t6 t5 t0 command address nop nop nop nop nop burst terminate nop t7 clk dq d out t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop d out d out d out burst terminate nop x = 1 cycle cl = 2 cl = 3 x = 2 cycles dont care transitioning data bank, col n read bank, col n d out d out d out d out note: 1. dqm is low. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram read operation pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 52 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. figure 23: alternating bank read accesses dont care undefined enable auto precharge t ch t cl t ck t ac t lz clk dq a10 t oh d out t cmh t cms t ah t as t ah t as t ah t as row row row row t oh d out t ac t oh t ac t oh t ac d out d out command t cmh t cms nop nop active nop read nop active t oh d out t ac t ac read enable auto precharge row active row bank 0 bank 0 bank 3 bank 3 bank 0 cke t ckh t cks column m column b 1 t0 t1 t2 t4 t3 t5 t6 t7 t8 t rp - bank 0 t ras - bank 0 t rcd - bank 0 t rcd - bank 0 cl - bank 0 t rcd - bank 3 cl - bank 3 t rc - bank 0 t rrd ba0, ba1 dqm address note: 1. for this example, bl = 4 and cl = 2. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram read operation pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 53 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. figure 24: read continuous page burst t ch t cl t ck t ac t lz t rcd cas latency cke clk dq a10 t oh d out t cmh t cms t ah t as t ah t as t ac t oh d out row row t hz t ac t oh d out t ac t oh d out t ac t oh d out t ac t oh d out ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) full page completed all locations within same row dont care undefined command t cmh t cms nop nop nop active nop read nop burst term nop nop ( ) ( ) ( ) ( ) nop ( ) ( ) ( ) ( ) t ah t as bank ( ) ( ) ( ) ( ) bank t ckh t cks ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) column m t0 t1 t2 t4 t3 t5 t6 tn + 1 tn + 2 tn + 3 tn + 4 ba0, ba1 dqm address full-page burst does not self-terminate. can use burst terminate command. note: 1. for this example, cl = 2. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram read operation pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 54 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. figure 25: read C dqm operation t ch t cl t ck t ac t ac t lz t rcd cl = 2 cke clk dq a10 t oh d out t cmh t cms t ah t as t ah t as t ah t as row bank row bank t hz t ac t lz t oh d out t oh d out t hz command t cmh t cms nop nop nop nop active nop read nop nop disable auto precharge enable auto precharge dont care undefined t ckh t cks column m t0 t1 t2 t4 t3 t5 t6 t7 t8 ba0, ba1 dqm address note: 1. for this example, bl = 4 and cl = 2. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram read operation pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 55 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. write operation write bursts are initiated with a write command, as shown in figure 10 (page 30). the starting column and bank addresses are provided with the write command and auto precharge is either enabled or disabled for that access. if auto precharge is ena- bled, the row being accessed is precharged at the completion of the burst. for the generic write commands used in the following figures, auto precharge is disabled. during write bursts, the first valid data-in element is registered coincident with the write command. subsequent data elements are registered on each successive positive clock edge. upon completion of a fixed-length burst, assuming no other commands have been initiated, the dq will remain at high-z and any additional input data will be ignored (see figure 26 (page 56)). a continuous page burst continues until termina- ted; at the end of the page, it wraps to column 0 and continues. data for any write burst can be truncated with a subsequent write command, and data for a fixed-length write burst can be followed immediately by data for a write command. the new write command can be issued on any clock following the previ- ous write command, and the data provided coincident with the new command ap- plies to the new command (see figure 27 (page 57)). data n + 1 is either the last of a burst of two or the last desired data element of a longer burst. mobile lpsdr devices use a pipelined architecture and therefore do not require the 2 n rule associated with a prefetch architecture. a write command can be initiated on any clock cycle following a previous write command. full-speed random write accesses within a page can be performed to the same bank, as shown in figure 28 (page 58), or each subsequent write can be performed to a different bank. figure 26: write burst clk dq d in t2 t1 t3 t0 command address nop nop dont care write d in nop bank, col n transitioning data note: 1. bl = 2. dqm is low. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram write operation pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 56 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. figure 27: write-to-write clk dq t2 t1 t0 command address nop write write bank, col n bank, col b d in d in d in dont care note: 1. dqm is low. each write command may be issued to any bank. data for any write burst can be truncated with a subsequent read command, and data for a fixed-length write burst can be followed immediately by a read command. after the read command is registered, data input is ignored and writes will not be executed (see figure 29 (page 58)). data n + 1 is either the last of a burst of two or the last desired data element of a longer burst. data for a fixed-length write burst can be followed by or truncated with a pre- charge command to the same bank, provided that auto precharge was not activated. a continuous-page write burst can be truncated with a precharge command to the same bank. the precharge command should be issued t wr after the clock edge at which the last desired input data element is registered. the auto precharge mode re- quires a t wr of at least one clock with time to complete, regardless of frequency. in addition, when truncating a write burst at high clock frequencies ( t ck < 15ns), the dqm signal must be used to mask input data for the clock edge prior to and the clock edge coincident with the precharge command (see figure 30 (page 59)). data n + 1 is either the last of a burst of two or the last desired data element of a longer burst. fol- lowing the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. in the case of a fixed-length burst being executed to completion, a precharge com- mand issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. the disadvant- age of the precharge command is that it requires that the command and address buses be available at the appropriate time to issue the command. the advantage of the precharge command is that it can be used to truncate fixed-length bursts or continu- ous page bursts. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram write operation pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 57 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. figure 28: random write cycles dont care clk dq d in t2 t1 t3 t0 command address write bank, col n d in d in d in write write write bank, col a bank, col x bank, col m note: 1. each write command can be issued to any bank. dqm is low. figure 29: write-to-read dont care clk dq t2 t1 t3 t0 command address nop write bank, col n d in d in d out read nop nop bank, col b nop d out t4 t5 note: 1. the write command can be issued to any bank, and the read command can be to any bank. dqm is low. cl = 2 for illustration. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram write operation pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 58 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. figure 30: write-to-precharge dont care dqm clk dq t2 t1 t4 t3 t0 command address bank a , col n t5 nop write precharge nop nop d in d in active t rp bank ( a or all) t wr bank a , row dqm dq command address bank a , col n nop write precharge nop nop active t rp bank ( a or all) t wr bank a , row t6 nop nop t wr @ t ck < 15ns t wr @ t ck 15ns d in d in note: 1. in this example dqm could remain low if the write burst is a fixed length of two. fixed-length write bursts can be truncated with the burst terminate command. when truncating a write burst, the input data applied coincident with the burst ter- minate command is ignored. the last data written (provided that dqm is low at that time) will be the input data applied one clock previous to the burst terminate com- mand. this is shown in figure 31 (page 60), where data n is the last desired data element of a longer burst. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram write operation pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 59 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. figure 31: terminating a write burst dont care clk dq t2 t1 t0 command address bank, col n write burst terminate next command d in address data transitioning data note: 1. dqm is low. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram write operation pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 60 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. figure 32: alternating bank write accesses dont care enable auto precharge t ch t cl t ck clk dq a10 t cmh t cms t ah t as t ah t as t ah t as row row row row command t cmh t cms nop nop active nop write nop nop active write enable auto precharge row active row bank 0 bank 0 bank 1 bank 1 bank 0 cke t ckh t cks column m column b t0 t1 t2 t4 t3 t5 t6 t7 t8 t9 t rp - bank 0 t ras - bank 0 t rcd - bank 0 t rcd - bank 0 t wr - bank 1 t wr - bank 0 t rcd - bank 1 t rc - bank 0 t rrd ba0, ba1 dqm address d in t dh t ds d in d in d in t dh t ds t dh t ds t dh t ds d in t dh t ds d in t dh t ds d in t dh t ds d in t dh t ds note: 1. for this example, bl = 4. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram write operation pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 61 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. figure 33: write C continuous page burst t ch t cl t ck t rcd cke clk a10 t cms t ah t as t ah t as row row full-page burst does not self-terminate. use burst terminate command to stop. 1, 2 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) full page completed dont care command t cmh t cms nop nop nop active nop write burst term nop nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dq d in t dh t ds d in d in d in t dh t ds t dh t ds t dh t ds d in t dh t ds t ah t as bank ( ) ( ) ( ) ( ) bank t cmh t ckh t cks ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) all locations within same row column m t0 t1 t2 t3 t4 t5 tn + 1 tn + 2 tn + 3 ba0, ba1 dqm address notes: 1. t wr must be satisfied prior to issuing a precharge command. 2. page left open; no t rp. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram write operation pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 62 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. figure 34: write C dqm operation dont care t ch t cl t ck t rcd cke clk dq a10 t cms t ah t as row bank row bank enable auto precharge d in t dh t ds d in d in t cmh command nop nop nop active nop write nop nop t cms t cmh t dh t ds t dh t ds t ah t as t ah t as disable auto precharge t ckh t cks column m t0 t1 t2 t3 t4 t5 t6 t7 ba0, ba1 dqm address note: 1. for this example, bl = 4. burst read/single write the burst read/single write mode is entered by programming the write burst mode bit (m9) in the mode register to a 1. in this mode, all write commands result in the access of a single column location (burst of one), regardless of the programmed burst length. read commands access columns according to the programmed burst length and se- quence, just as in the normal mode of operation (m9 = 0). 128mb: 8 meg x 16, 4 meg x 32 mobile sdram write operation pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 63 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. precharge operation the precharge command (see figure 11 (page 31)) is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a sub- sequent row access some specified time ( t rp) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged (a10 = low), inputs ba0 and ba1 select the bank. when all banks are to be precharged (a10 = high), inputs ba0 and ba1 are treated as dont care. after a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. auto precharge auto precharge is a feature that performs the same individual-bank precharge func- tion described previously, without requiring an explicit command. this is accomplish- ed by using a10 to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/row that is addressed with the read or write com- mand is automatically performed upon completion of the read or write burst, except in the continuous page burst mode where auto precharge does not apply. in the specific case of write burst mode set to single location access with burst length set to continu- ous, the burst length setting is the overriding setting and auto precharge does not apply. auto precharge is nonpersistent in that it is either enabled or disabled for each individu- al read or write command. auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. another command cannot be issued to the same bank until the precharge time ( t rp) is completed. this is determined as if an explicit precharge command was is- sued at the earliest possible time, as described for each burst type in the burst type (page 41) section. this device supports t ras lock-out. in the case of a single read with auto precharge, or a single write with auto precharge, issued at t rcd (min), the internal precharge will be delayed until t ras (min) has been satisfied. micron sdram supports concurrent auto precharge; cases of concurrent auto pre- charge for reads and writes are defined below. read with auto precharge interrupted by a read (with or without auto precharge) a read to bank m will interrupt a read on bank n following the programmed cas la- tency. the precharge to bank n begins when the read to bank m is registered (see figure 35 (page 65)). read with auto precharge interrupted by a write (with or without auto precharge) a write to bank m will interrupt a read on bank n when registered. dqm should be used two clocks prior to the write command to prevent bus contention. the pre- charge to bank n begins when the write to bank m is registered (see figure 36 (page 66)). write with auto precharge interrupted by a read (with or without auto precharge) a read to bank m will interrupt a write on bank n when registered, with the data-out appearing cl later. the precharge to bank n will begin after t wr is met, where t wr be- gins when the read to bank m is registered. the last valid write to bank n will be data- in registered one clock prior to the read to bank m (see figure 41 (page 71)). 128mb: 8 meg x 16, 4 meg x 32 mobile sdram precharge operation pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 64 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. write with auto precharge interrupted by a write (with or without auto precharge) a write to bank m will interrupt a write on bank n when registered. the precharge to bank n will begin after t wr is met, where t wr begins when the write to bank m is registered. the last valid data write to bank n will be data registered one clock prior to a write to bank m (see figure 42 (page 71)). figure 35: read with auto precharge interrupted by a read dont care clk dq d out t2 t1 t4 t3 t6 t5 t0 command read - ap bank n nop nop nop nop d out d out d out nop t7 bank n cl = 3 (bank m ) bank m address idle nop bank n , col a bank m , col d read - ap bank m internal states t page active read with burst of 4 interrupt burst, precharge page active read with burst of 4 precharge rp - bank n t rp - bank m cl = 3 (bank n ) note: 1. dqm is low. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram precharge operation pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 65 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. figure 36: read with auto precharge interrupted by a write clk dq d out t2 t1 t4 t3 t6 t5 t0 command nop nop nop nop d in d in d in d in nop t7 bank n bank m address idle nop dqm 1 bank n , col a bank m , col d write - ap bank m internal states t page active read with burst of 4 interrupt burst, precharge page active write with burst of 4 write-back rp - bank n t wr - bank m cl = 3 (bank n ) read - ap bank n dont care note: 1. dqm is high at t2 to prevent d out a + 1 from contending with d in d at t4. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram precharge operation pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 66 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. figure 37: read with auto precharge t ch t cl t ck t ac t lz t rp t ras t rcd cl = 2 t rc cke clk dq a10 t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row bank bank row row bank t hz t oh d out m + 3 t ac t oh t ac t oh t ac d out m + 2 d out m + 1 command t cmh t cms nop nop nop nop active nop read nop active enable auto precharge dont care undefined t ckh t cks column m t0 t1 t2 t4 t3 t5 t6 t7 t8 ba0, ba1 dqm address note: 1. for this example, bl = 4 and cl = 2. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram precharge operation pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 67 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. figure 38: read without auto precharge t ch t cl t ck t ac t lz t rp t ras t rcd cl = 2 t rc cke clk dq a10 t oh d out t cmh t cms t ah t as t ah t as t ah t as row row bank bank(s) bank row row bank t hz t oh d out t ac t oh t ac t oh t ac d out d out command t cmh t cms precharge nop nop nop active nop read nop active disable auto precharge single bank all banks dont care undefined t ckh t cks column m t0 t1 t2 t4 t3 t5 t6 t7 t8 ba0, ba1 dqm address note: 1. for this example, bl = 4, cl = 2, and the read burst is followed by a manual precharge. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram precharge operation pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 68 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. figure 39: single read with auto precharge t ch t cl t ck t ac t oh t lz t rp t ras t rcd cl = 2 t rc cke clk dq a10 d out t cmh t cms t ah t as t ah t as t ah t as row row bank bank row row bank command t cmh t cms nop nop nop nop active nop read active enable auto precharge dont care undefined t ckh t cks column m t0 t1 t2 t4 t3 t5 t6 t7 ba0, ba1 dqm address note: 1. for this example, bl = 1 and cl = 2. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram precharge operation pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 69 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. figure 40: single read without auto precharge all banks t ch t cl t ck t ac t lz t rp t ras t rcd cl = 2 t rc cke clk dq a10 t oh d out t cmh t cms t ah t as t ah t as t ah t as row row bank bank(s) bank row row bank t hz command t cmh t cms nop nop nop precharge active nop read active nop disable auto precharge single bank dont care undefined t ckh t cks column m t0 t1 t2 t4 t3 t5 t6 t7 t8 ba0, ba1 dqm address note: 1. for this example, bl = 1, cl = 2, and the read burst is followed by a manual precharge. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram precharge operation pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 70 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. figure 41: write with auto precharge interrupted by a read dont care clk dq t2 t1 t4 t3 t6 t5 t0 command write - ap bank n nop nop nop nop d in d in nop nop t7 bank n bank m address bank n , col a bank m , col d read - ap bank m internal states t page active write with burst of 4 interrupt burst, write-back precharge page active read with burst of 4 t t rp - bank m d out d out cl = 3 (bank m ) rp - bank n wr - bank n note: 1. dqm is low. figure 42: write with auto precharge interrupted by a write dont care clk dq t2 t1 t4 t3 t6 t5 t0 command write - ap bank n nop nop nop nop d in d in d in d in d in d in d in nop t7 bank n bank m address nop bank n , col a bank m , col d write - ap bank m internal states t page active write with burst of 4 interrupt burst, write-back precharge page active write with burst of 4 write-back wr - bank n t rp - bank n t wr - bank m note: 1. dqm is low. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram precharge operation pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 71 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. figure 43: write with auto precharge enable auto precharge t ch t cl t ck t rp t ras t rcd t rc cke clk dq a10 t cmh t cms t ah t as row bank row bank t wr dont care d in t dh t ds d in d in d in command t cmh t cms nop nop nop active nop write nop nop nop row bank row t ah t as t ah t as t dh t ds t dh t ds t dh t ds t ckh t cks column m t0 t1 t2 t4 t3 t5 t6 t7 t8 t9 dqm ba0, ba1 address active note: 1. for this example, bl = 4. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram precharge operation pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 72 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. figure 44: write without auto precharge disable auto precharge all banks t ch t cl t ck t rp t ras t rcd t rc cke clk dq a10 t cmh t cms t ah t as row bank bank row bank t wr dont care d in t dh t ds d in d in d in command t cmh t cms nop nop nop active nop write precharge nop nop row bank row t ah t as t ah t as t dh t ds t dh t ds t dh t ds single bank t ckh t cks column m t0 t1 t2 t4 t3 t5 t6 t7 t8 t9 dqm ba0, ba1 address active note: 1. for this example, bl = 4 and the write burst is followed by a manual precharge. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram precharge operation pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 73 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. figure 45: single write with auto precharge enable auto precharge t ch t cl t ck t rp t ras t rcd t rc cke clk dq a10 t cmh t cms t ah t as row bank row bank t wr dont care d in t dh t ds command t cmh t cms nop nop nop active nop write nop nop row bank row t ah t as t ah t as t ckh t cks column m t0 t1 t2 t4 t3 t5 t6 t7 t8 dqm ba0, ba1 address active note: 1. for this example, bl = 1. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram precharge operation pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 74 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. figure 46: single write without auto precharge t ch t cl t ck t rp t ras t rcd t wr t rc cke clk dq a10 t cmh t cms t ah t as t ah t as t ah t as row bank bank bank row row bank command t cmh t cms nop nop nop precharge active nop write active nop disable auto precharge dont care t ckh t cks column m t0 t1 t2 t4 t3 t5 t6 t7 t8 ba0, ba1 dqm address d in t dh t ds all banks single bank note: 1. for this example, bl = 1 and the write burst is followed by a manual precharge. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram precharge operation pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 75 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. auto refresh operation the auto refresh command is used during normal operation of the device to refresh the contents of the array. this command is nonpersistent, so it must be issued each time a refresh is required. all active banks must be precharged prior to issuing an auto refresh command. the auto refresh command should not be issued until the min- imum t rp is met following the precharge command. addressing is generated by the internal refresh controller. this makes the address bits dont care during an auto refresh command. after the auto refresh command is initiated, it must not be interrupted by any exe- cutable command until t rfc has been met. during t rfc time, command inhibit or nop commands must be issued on each positive edge of the clock. the sdram re- quires that every row be refreshed each t ref period. providing a distributed auto refresh commandcalculated by dividing the refresh period ( t ref) by the number of rows to be refreshedmeets the timing requirement and ensures that each row is re- freshed. alternatively, to satisfy the refresh requirement a burst refresh can be em- ployed after every t ref period by issuing consecutive auto refresh commands for the number of rows to be refreshed at the minimum cycle rate ( t rfc). 128mb: 8 meg x 16, 4 meg x 32 mobile sdram auto refresh operation pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 76 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. figure 47: auto refresh mode all banks dont care t ch t cl t ck cke clk dq t rfc ( ) ( ) ( ) ( ) t rp ( ) ( ) ( ) ( ) command t cmh t cms nop nop ( ) ( ) ( ) ( ) bank active auto refresh ( ) ( ) ( ) ( ) nop nop precharge precharge all active banks auto refresh t rfc high-z bank(s) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t ah t as t ckh t cks nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) row ( ) ( ) ( ) ( ) single bank a10 row ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t0 t1 t2 tn + 1 to + 1 ba0, ba1 address dqm ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) note: 1. back-to-back auto refresh commands are not required. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram auto refresh operation pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 77 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. self refresh operation the self refresh mode can be used to retain data in the device, even when the rest of the system is powered down. when in self refresh mode, the device retains data without external clocking. the self refresh command is initiated like an auto refresh command, except cke is disabled (low). after the self refresh command is regis- tered, all the inputs to the device become dont care with the exception of cke, which must remain low. after self refresh mode is engaged, the device provides its own internal clocking, ena- bling it to perform its own auto refresh cycles. the device must remain in self refresh mode for a minimum period equal to t ras and remains in self refresh mode for an indefinite period beyond that. the procedure for exiting self refresh requires a sequence of commands. first, clk must be stable prior to cke going back high. (stable clock is defined as a signal cycling within timing constraints specified for the clock ball.) after cke is high, the device must have nop commands issued for a minimum of two clocks for t xsr because time is required for the completion of any internal refresh in progress. upon exiting the self refresh mode, auto refresh commands must be issued accord- ing to the distributed refresh rate ( t ref/refresh row count) as both self refresh and auto refresh utilize the row refresh counter. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram self refresh operation pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 78 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. figure 48: self refresh mode all banks t ch t cl t ck t rp cke clk dq enter self refresh mode precharge all active banks t xsr clk stable prior to exiting self refresh mode exit self refresh mode (restart refresh time base) ( ) ( ) ( ) ( ) ( ) ( ) dont care command t cmh t cms auto refresh precharge nop nop bank(s) high-z t cks t ah t as auto refresh t ckh t cks a10 t0 t1 t2 tn + 1 to + 1 to + 2 ba0, ba1 dqm address ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) single bank note: 1. each auto refresh command performs a refresh cycle. back-to-back commands are not required. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram self refresh operation pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 79 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. power-down power-down occurs if cke is registered low coincident with a nop or command in- hibit when no accesses are in progress. if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power- down deactivates the input and output buffers, excluding cke, for maximum power savings while in standby. the device cannot remain in the power-down state longer than the refresh period (64ms) because no refresh operations are performed in this mode. the power-down state is exited by registering a nop or command inhibit with cke high at the desired clock edge (meeting t cks). figure 49: power-down mode all banks t ch t cl t ck two clock cycles cke clk dq all banks idle, enter power-down mode precharge all active banks input buffers gated off while in power-down mode exit power-down mode ( ) ( ) dont care t cks t cks command t cmh t cms precharge nop nop active nop ( ) ( ) ( ) ( ) all banks idle ba0, ba1 bank bank(s) ( ) ( ) ( ) ( ) high-z t ah t as t ckh t cks dqm ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) address row ( ) ( ) ( ) ( ) single bank a10 row ( ) ( ) ( ) ( ) t0 t1 t2 tn + 1 tn + 2 ( ) ( ) note: 1. violating refresh requirements during power-down may result in a loss of data. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram power-down pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 80 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. deep power-down deep power-down mode is a maximum power-saving feature achieved by shutting off the power to the entire device memory array. data on the memory array will not be re- tained after deep power-down mode is executed. deep power-down mode is entered by having all banks idle, with cs# and we# held low with ras# and cas# high at the rising edge of the clock, while cke is low. cke must be held low during deep power- down. to exit deep power-down mode, cke must be asserted high. upon exiting deep power- down mode, a full initialization sequence is required. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram deep power-down pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 81 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. clock suspend the clock suspend mode occurs when a column access/burst is in progress and cke is registered low. in the clock suspend mode, the internal clock is deactivated, freezing the synchronous logic. for each positive clock edge on which cke is sampled low, the next internal positive clock edge is suspended. any command or data present on the input balls when an in- ternal clock edge is suspended will be ignored; any data present on the dq balls remains driven; and burst counters are not incremented, as long as the clock is suspended. exit clock suspend mode by registering cke high; the internal clock and related opera- tion will resume on the subsequent positive clock edge. figure 50: clock suspend during write burst dont care d in command address write bank, col n d in nop nop clk t2 t1 t4 t3 t5 t0 cke internal clock nop d in d in note: 1. for this example, bl = 4 or greater, and dqm is low. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram clock suspend pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 82 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. figure 51: clock suspend during read burst dont care clk dq d out t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop bank, col n nop d out d out d out cke internal clock nop note: 1. for this example, cl = 2, bl = 4 or greater, and dqm is low. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram clock suspend pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 83 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. figure 52: clock suspend mode t ch t cl t ck t ac t lz dqm clk dq a10 t oh d out t ah t as t ah t as t ah t as bank t dh d in t ac t hz d out command t cmh t cms nop nop nop nop nop read write dont care undefined cke t cks t ckh bank column m t ds d in nop t ckh t cks t cmh t cms column e t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 ba0, ba1 address note: 1. for this example, bl = 2, cl = 3, and auto precharge is disabled. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram clock suspend pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 84 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. revision history rev. g, production C 10/09 ? deleted "(8192 rows)" from t ref parameter in electrical characteristics and recom- mended ac operating conditions table. rev. f, production C 8/09 ? updated format. rev. e, production C 4/09 ? ac functional characteristics table: updated note 9. rev. d, production C 10/08 ? changed to production status. rev. c, preliminary C 9/08 ? ac functional characteristics table: corrected speed grades column headings. rev. b, preliminary C 6/08 ? changed to preliminary status. rev. a, advance C 4/08 ? initial release. revision history for commands, operations, and timing diagrams update C 10/08 ? deep power-down: added description for exiting dpd. update C 7/08 ? updated address/data range presentation to industry-standard presentation. ? replaced mode register set with lmr as appropriate. ? truth table C current state bank n, command to bank m, note 13: added missing m. ? mode register: corrected presentation of mode register bits. ? partial-array self refresh (pasr): updated refresh options presentation. update C 5/08 ? auto precharge: added fourth paragraph regarding t ras lock-out. ? single read with auto precharge: updated figure. ? write without auto precharge: updated note to bl = 4. ? single write with auto precharge: updated figure. ? single write without auto precharge: updated figure. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram revision history pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 85 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. update C 4/08 ? added three-quarter drive strength content. 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 www.micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. 128mb: 8 meg x 16, 4 meg x 32 mobile sdram revision history pdf: 09005aef832ff1ea 128mb_mobile_sdram_y35m.pdf - rev. g 10/09 en 86 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. |
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